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Browse Prior Art Database

Stackable Flex Packaging of Chips

IP.com Disclosure Number: IPCOM000115619D
Original Publication Date: 1995-Jun-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Mara, K: AUTHOR [+4]

Abstract

Semiconductor device chips are connected to flexible tape circuits via wire bond or controlled collapse chip connection (C4) and folded into a stack for dense packaging and connection to a next level of card or board wiring. A few examples of the many high density packaging configurations afforded by the basic method of mounting chips on flexible wiring tape are described.

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This is the abbreviated version, containing approximately 94% of the total text.

Stackable Flex Packaging of Chips

      Semiconductor device chips are connected to flexible tape
circuits via wire bond or controlled collapse chip connection (C4)
and folded into a stack for dense packaging and connection to a next
level of card or board wiring.  A few examples of the many high
density packaging configurations afforded by the basic method of
mounting chips on flexible wiring tape are described.

      Referring to Fig. 1.1 and cross-sectional view, Fig 1.2,
semiconductor chips 2 are connected in a linear array to wiring (not
shown) on both sides of flexible tape 4.  As shown in Fig. 1.3, the
flexible wiring, with attached chips, may be folded to form a stack
of chips.  Thermally conductive tape or potting compound may be used
to hold the chip stack together and leads may be brought out from the
stack for connection to a next wiring level in a variety of ways.
Wider tape having several rows of chips similarly disposed may be
used for larger chip packages.

      Referring to Fig. 2.1, five chips 2 are shown connected to
cross shaped flex-wiring 4.  In Fig. 2.2, a series of mounted chips
on successively larger wiring crosses have legs of the crosses bent
and leads attached to a next level of package 6.

      Higher volume packing density is achieved as follows.
Referring to Fig. 3.1, single chips 2 are connected to centers of
cross-shaped flex wiring 4.  Wiring crosses 4 are cut and bent
appropriately to nest chips 2 as shown in Fig. 3...