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Word-Wise Traceback of Trellis Code Viterbi Detectors

IP.com Disclosure Number: IPCOM000115648D
Original Publication Date: 1995-Jun-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 99K

Publishing Venue

IBM

Related People

Fredrickson, L: AUTHOR

Abstract

The architecture described here provides a method for organizing the path memory in Viterbi detector in such a way that reduces the overall complexity and power consumption of the hardware requirement. In this architecture, groups of ten bit decisions are traced back a word at a time from the most recent ten bit decisions to a most likely path several ten bit blocks ago, thus minimizing delay and power consumption. Fig. 1 illustrates the typical local structure of a trellis code detector. The vertices represent detector states as a function of time, and this structure repeats itself every ten bits. A maximum likelihood detector recursively chooses the most likely path leading to each state, and calculates a state metric related to the likelihood of that path.

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Word-Wise Traceback of Trellis Code Viterbi Detectors

      The architecture described here provides a method for
organizing the path memory in Viterbi detector in such a way that
reduces the overall complexity and power consumption of the hardware
requirement.  In this architecture, groups of ten bit decisions are
traced back a word at a time from the most recent ten bit decisions
to a most likely path several ten bit blocks ago, thus minimizing
delay and power consumption.  Fig. 1 illustrates the typical local
structure of a trellis code detector.  The vertices represent
detector states as a function of time, and this structure repeats
itself every ten bits.  A maximum likelihood detector recursively
chooses the most likely path leading to each state, and calculates a
state metric related to the likelihood of that path.  Every ten bits,
four most likely survivor paths to the four terminal states are
found.

      It is assumed that the ten bit path memories for one copy of
the local trellis structure are determined by known methods, such as
register exchange, and these ten bit memories are denoted GPMO
through GPM3.  In order to trace over a multiple of these memories,
the source state for a ten bit path leading to a given sink state
must be found.  These can be found using a circuit such as that shown
in Fig. 2.  In Fig. 1, the source and sink states are designated by a
two-component vector (V,M), as shown.  The first bit decision leading
to states 1 through 4 in Fig. 1 is designated D(1) through D(4),
respectively, and is stored.  The circuit in Fig. 2 is used to
determine, using the value of V for a sink state and the ten bits of
stored path memory, the value of V and M...