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Mechanism for Multiple Source Access of Queues and Stacks

IP.com Disclosure Number: IPCOM000115658D
Original Publication Date: 1995-Jun-01
Included in the Prior Art Database: 2005-Mar-30

Publishing Venue

IBM

Related People

Ouchi, NK: AUTHOR

Abstract

The objective of this disclosure is to describe a bus attached buffer that performs the functions of multiple FIFO queues and LIFO stacks in a very modular form so that it may be used as one of the elements to create complex, multi-adapter systems to serve as the input-output controller for processor systems or for devices such as DASD, tape, TP, storage systems. The key innovation is the use of the address parameter normally used to specify a memory location as the parameter to specify an individual queue or stack. The real address pointers are managed and checked by the disclosed mechanism. Thus, the interface to the queues and stacks is very simple: the bus attached source/consumer need only read or write to the queue/stack address with a string of data.

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Mechanism for Multiple Source Access of Queues and Stacks

      The objective of this disclosure is to describe a bus attached
buffer that performs the functions of multiple FIFO queues and LIFO
stacks in a very modular form so that it may be used as one of the
elements to create complex, multi-adapter systems to serve as the
input-output controller for processor systems or for devices such as
DASD, tape, TP, storage systems.  The key innovation is the use of
the address parameter normally used to specify a memory location as
the parameter to specify an individual queue or stack.  The real
address pointers are managed and checked by the disclosed mechanism.
Thus, the interface to the queues and stacks is very simple: the bus
attached source/consumer need only read or write to the queue/stack
address with a string of data.  The disclosed mechanism takes care of
the housekeeping and checking for over/under run.

      Most DASD, tape, TP and other control units have hardware used
in conjunction with a programmable controller to aid in performing
the data transfer functions of the control unit.  There are many
hardware designs and chips that perform FIFO and LIFO functions for
data rate matching or buffering.  These are limited in size and
function and are called two-port buffers, or similar names.  Many
control units have larger buffers with combined hardware and
microcode control that are used primarily in data transfer and are
called Automatic Data Transfer, ADT, hardware.  In most ADT designs,
the hardware generates storage addresses for a Random Access Memory,
RAM, to fetch or store data directly into the RAM.  The ADT hardware
performs the incrementing of the storage pointers and may check that
the pointers do not overrun each other or perform other functions to
insure the integrity of the data.

      The functions of QUEUES, a FIFO buffer, and STACKS, a LIFO
buffer, are illustrated in Fig. 1.  In a linear address space such as
a RAM, the FIFO is filled by a writer using a WRITE pointer and
emptied by a READER using a READ pointer.  The WRITE pointer precedes
the READ pointer and the data between is considered to be valid.  As
data is written and read, the two pointers and the space with valid
data progresses through the RAM address space.  This is illustrated
in Fig. 1a.  Since RAM is not unlimited, the FIFO uses a limited RAM
address.  This is shown in Fig. 1b.  When either WRITE or READ
pointers reach the upper boundary as specified by the TOP pointer, it
is set to the lower boundary as specified by the BOTTOM pointer.
This is called wrap-around.  The data between the READ pointer to the
TOP pointer and between the BOTTOM pointer to the WRITE pointer are
valid.  This is shown in Fig. 1c.  A LIFO buffer is shown in Fig. 1d.
Data are written at the WRITE pointer and later read at the READ
pointer.  The TOP and BOTTOM pointers are used to limit the RAM
address space used.  The LIFO is full when the WRITE p...