Browse Prior Art Database

Direct Memory Access Paging and Remote DRAM Access Through an Optimized Memory Mapping Mechanism

IP.com Disclosure Number: IPCOM000115667D
Original Publication Date: 1995-Jun-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 190K

Publishing Venue

IBM

Related People

Andrews, LP: AUTHOR [+5]

Abstract

Disclosed is a mechanism and Method to allow for simplified hardware address specifications when generating Direct Memory Access (DMA) requests or remote access for DRAM implemented using a Transparent Memory Mapping Mechanism.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 41% of the total text.

Direct Memory Access Paging and Remote DRAM Access Through an Optimized
Memory Mapping Mechanism

      Disclosed is a mechanism and Method to allow for simplified
hardware address specifications when generating Direct Memory Access
(DMA) requests or remote access for DRAM implemented using a
Transparent Memory Mapping Mechanism.

      This disclosure adds additional capability which minimizes the
amount of code required to interface to the DRAM when this type of
memory-mapping is used.

      In prior implementations of this type of memory mapping, when
the Digital Signal Processors wished to DMA data to or from the DRAM
to host storage (or vice-versa) it was necessary to provide code to
take the logical address and page register information for the data
to be transferred, use it to calculate the corresponding physical
address, check if the request would cross a physical memory segment
boundary and, if so, split it into smaller requests, and only then
build the actual request block(s) for use by the DMA hardware.
Similarly, when the host wished to access DRAM directly the actual
physical address was required.  If this data then needed to be
correlated to the logical memory space as known to the DSP, it was
necessary to convert the physical address back to a logical address
and related page register information.  Additionally, when the intent
was to read or write a range of logical DRAM space, it was necessary
to ensure that the range did not cross a physical memory segment
boundary.

      A further complication of the prior implementations is that if
there was a desire to port code written for one implementation to run
in a system having a different physical memory layout (i.e.,
different sizes or numbers of segments), it was necessary to rewrite
those portions of code which performed the logical-to-physical
address conversions and which verified that requests did not cross
physical segment boundries.

SUMMARY OF INVENTION - The present invention describes a method
whereby address conversions and physical segment boundary
verifications are no longer needed.  This eliminates lines of code
and improves performance.  Additionally, this mechanism reduces the
size of the address bus used for DRAM accesses to/from the host.  It
also makes it much easier to port code from one system to another
since it is no longer necessary for the code to be aware of physical
memory segment boundaries or to know which physical addresses are
mapped to which logical address ranges.  In some instances no changes
would be required.  In other instances, only the values written to
the Page Registers would change.

Features of this disclosure are listed below:
  1.  Automatic DMA address translation based on Page Register.
  2.  Automatic Host DSP address translation based on Page Register.
  3.  DSP Kernel can be optimized since it only needs to keep track
of
       current Page register, not physical addresses and segment
      ...