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Synchronization Sequence Detection using a Modified Trellis Code Viterbi Detector

IP.com Disclosure Number: IPCOM000115671D
Original Publication Date: 1995-Jun-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 216K

Publishing Venue

IBM

Related People

Fredrickson, L: AUTHOR

Abstract

The disclosed architecture described provides a frame synchronization method in Viterbid detectors with time-varying control and time-varying trelis code, without increasing the length of the sync word and with only a minor increase in hardware complexity. A modified Viterbi trellis detector is used to search for the synchronization sequence. The modification involves the periodic deletion of certain edges from the detector trellis for all of the implemented TCPR codes.

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Synchronization Sequence Detection using a Modified Trellis Code
Viterbi Detector

      The disclosed architecture described provides a frame
synchronization method in Viterbid detectors with time-varying
control and time-varying trelis code, without increasing the length
of the sync word and with only a minor increase in hardware
complexity.  A modified Viterbi trellis detector is used to search
for the synchronization sequence.  The modification involves the
periodic deletion of certain edges from the detector trellis for all
of the implemented TCPR codes.

      The synch detector is designed for use on a PR4 (1-D(2))
channel and is designed to distinguish a certain synch sequence from
the timing acquisition (T) pattern and shifted versions of itself.
The PR4 channel is deinterleaved into two dicode (1-D) channels for
the even and odd samples prior to detection.

      The implemented synch scheme assumes that a reliable
lock-to-data (LTD) signal activates the synch processing during
reception of the T pattern.  The synch detector performs
pre-detection processing of the T pattern samples to assign branch
metrics and align the deinterleaved data streams.  After
pre-processing, synch detection is performed by examining the path
memory of the Viterbi detector, and making a majority logic decision
on the presence of a sufficient number of attributes which
distinguish the synch pattern from the T pattern.  SYNCH DETECTION
PRE-PROCESSING - The T pattern results in the noiseless samples {+1,
+1, -1, -1, +1, +1, -1, -1, +1, +1,,...} at the output of the
channel.  During reception of the T pattern, each 1-D detector
receives the samples {+1, -1, +1, -1, +1, -1,....} corrupted by
noise.  Denoting the ith received sample by y[i], the receiver uses
the linearized branch metrics:
  b(i,-1)=0.5+y(i), b(i,0)=0, b(i,+1)=0.5-y(i),
  to judge the relative distance from the received sample to the
noiseless sample of -1, 0, or +1, respectively.  In each interleave,
the receiver having no knowledge of the particular phase of the T
pattern in each of the 1-D interleaves, begins with the two single
state subtrellises of Fig. 1 with initial state metrics, S and S',
initially reset to 0.

      Please REVIEW the following paragraph.

      Alternating b(i,+1,)b(i,-1) branch metric are assigned to the
successive branches shown succeeding from state 2, and resulting
state metrics, S and S', are accumulated.  For convenience in Fig. 1
and subsequent figures, a horizontal branch ending in a black state
denotes a branch with an ideal noiseless sample of +1, while a
horizontal branch ending in a white state denotes a branch with an
ideal noiseless sample of -1.

      After n +2k received samples, the expected state metric
accumulated for each state is dependent on whether the assumed
initial branch metrics were correct, i.e.,
    E(S/ branch metric assignment is correct)=-n/2=-k,
  while
    E(S/ branch metric assignment is i...