Browse Prior Art Database

Elimination of Seed Layer Electrical Shorts

IP.com Disclosure Number: IPCOM000115745D
Original Publication Date: 1995-Jun-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Lee, R: AUTHOR [+2]

Abstract

During the fabrication of inductive thin film heads, both for read/write and/or MR applications, the need to completely remove electroplating seed layer is needed.

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This is the abbreviated version, containing approximately 77% of the total text.

Elimination of Seed Layer Electrical Shorts

      During the fabrication of inductive thin film heads, both for
read/write and/or MR applications, the need to completely remove
electroplating seed layer is needed.

      The seed layer, which could be either NiFe or CrCu materials,
will comformably cover all structures present on the substrates.
Some of these structures can have height and wall profiles that could
cause some metallic residue to be left behind after the ionic plasma
removal step (sputter etch, or ion milling).  The masking effect of
said steps also necessitates extending the vacuum removal cycle, thus
causing larger redeposition against vertical surfaces such as pole
tips.

      This invention generates via the standard insulation process
steps a localized region on said resist structures where the hard
baked resist will end up with less of a wall angle, thus enabling the
vacuum seed layer removal step to completely remove all residues.

      By introducing artifacts between critical regions, such as
between leads or between leads and ferromagnetic elements, we turn
such artifacts as localized free of residue regions.  To make such
artifacts, pointy images which reach at the very narrow tip the
photolithographic resolution of the photo tooling are added to the
insulation edges.  The diffraction limited optics will create a
gradually decreased resist thickness towards the tip of said images.
After high temperature polymerization, while th...