Browse Prior Art Database

Chiplets' Interconnections Pathway Control and Merging of Master and Slave Buses

IP.com Disclosure Number: IPCOM000115748D
Original Publication Date: 1995-Jun-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 159K

Publishing Venue

IBM

Related People

Marenin, GB: AUTHOR

Abstract

This innovation merges the two unidirectional master buses with the same two slave buses for interconnecting the many macros to each other on the product chips. This reduces the Common Macro Interface Pathway logic in half with nearly a similar saving in the hundreds of bus lines' chip wiring while keeping the same performance. The proposed algorithm and the simple bus multiplexing structure makes it possible for the four buses between the chiplet macros to be combined into two unidirectional and shared buses for masters and slaves.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 46% of the total text.

Chiplets' Interconnections Pathway Control and Merging of Master
and Slave Buses

      This innovation merges the two unidirectional master buses with
the same two slave buses for interconnecting the many macros to each
other on the product chips.  This reduces the Common Macro Interface
Pathway logic in half with nearly a similar saving in the hundreds of
bus lines' chip wiring while keeping the same performance.  The
proposed algorithm and the simple bus multiplexing structure makes it
possible for the four buses between the chiplet macros to be combined
into two unidirectional and shared buses for masters and slaves.
Since for most of the time only one bus is used, depending on the
data transfer direction (read or write), and never more than two
buses communicate at any instant between any master and slave macros
through the pathway, this invention eliminates the four buses'
wasteful redundancy of at least 100%.

      Present interconnections of many macros to each other on the
product chips is done with a defined Common Macro Interface (CMI).
The communication logic is separated into two unidirectional and
independent master and two more repeated slave buses.  This new
invention goes a big step further by reducing the hardware and wiring
in nearly half (removing the original duplication).  All this is
accomplished while preserving the same CMI original protocol.

      Each chiplet normally has a master and a slave interface.
There can be chiplets with just a master (e.g., processor) or just a
slave (e.g., memory) interface.  Most chiplets can only execute
either a master or a slave function (e.g., bidirectional local
communication bus) at any given time.  If on occasion, master
operations can be overlapped in parallel with its own slave data
transfers, then the chiplet has the complete intelligence to share
the unidirectional common buses independent of the interconnecting
pathway arbitrations and controls.  The concurrent bus sharing is
fully controlled by the CMI 3 bit response bus (RpX) providing 8
directing conditions.  The address is always placed on the outgoing
OBx bus for the duration of any master originating its RqX request
signal and is then transferred on the first cycle of every slave
acknowledge (AkX) connection completion.  At the end of this address
cycle, the originating master drops its RqX request and write or read
data transfer starts and continues until the responding slave removes
its AkX acknowledge signal.

      The common master/slave buses also simplify the shared data
flow by avoiding multiplexing and demultiplexing between the master
and the slave redundant buses.  Since masters can only originate data
transfers and slaves can only accept commands with addresses, every
master always owns the output bus and every slave the input bus
unless loaned for specified durations between themselves.  With this
basic concept, every master can start any write or read operation
with any slave b...