Browse Prior Art Database

P-OR Domino Gate

IP.com Disclosure Number: IPCOM000115797D
Original Publication Date: 1995-Jun-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Grohoski, GF: AUTHOR [+4]

Abstract

High performance CMOS CPUs typically rely on some type of dynamic logic, such as domino, to reduce logic delay. Fig. 1 depicts a typical domino gate. It consists of an N-tree, a ratioed inverter to quickly sense discharge of the N-tree, and provide noise immunity and gain, and a precharge device to precharge the dynamic node. The logic funtion, F, of the gate is: F = (A1 & A2) | (B1 & B2) | (C1 & C2);

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P-OR Domino Gate

      High performance CMOS CPUs typically rely on some type of
dynamic logic, such as domino, to reduce logic delay.  Fig. 1 depicts
a typical domino gate.  It consists of an N-tree, a ratioed inverter
to quickly sense discharge of the N-tree, and provide noise immunity
and gain, and a precharge device to precharge the dynamic node.  The
logic funtion, F, of the gate is:
  F = (A1 & A2) | (B1 & B2) | (C1 & C2);

      One problem with domino circuits is that during worst-case
evaluation patterns, only one leg must discharge the entire N-tree.
Thus, the evaluate speed is affected by parasitic source and drain
diffusion capacitances of inactive legs whose topmost transistors are
conducting.

The additional legs of the N-tree form an logic OR function.  One can
speed up this function by partitioning the N-tree into several
individual
legs, replacing the output inverter by a ratioed NAND-gate, and
connecting each of the original legs to one input of the NAND gate
(Fig. 2).

      In this way each leg only sees its own parasitic capacitancees
during discharge.  The output NAND gate can be ratioed (just as the
original inverter was) to achieve the desired switch point.  AS/X
simulation studies have shown that this configuration performs 20-40%
faster than typical domino gates with a single monolithic N-tree.