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High-Speed Circuit Technique for BiFET Logic and System Application

IP.com Disclosure Number: IPCOM000115801D
Original Publication Date: 1995-Jun-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 95K

Publishing Venue

IBM

Related People

Chung, PW: AUTHOR [+5]

Abstract

Disclosed is a new circuit technique is developed to eliminate delay problems associated with the use of CMOS logic gates in the design of high speed processors. This technique is applied to the design of a flash A/D encoder which is described below.

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High-Speed Circuit Technique for BiFET Logic and System Application

      Disclosed is a new circuit technique is developed to eliminate
delay problems associated with the use of CMOS logic gates in the
design of high speed processors.  This technique is applied to the
design of a flash A/D encoder which is described below.

      In the conventional flash analog-to-digital design, the outputs
of the 2**N-1 latches are encoded by combinatorial logic to the N
bits digital outputs.  Very often the conversion time of this type of
A/D is degraded due to the logic circuit propagation delay.  To
improve the conversion time of this flash A/D design, the encoding
method has to be altered.  One way to encode the 2**N-1 bits to N
bits is to employ the new encoder described below.

      It is commonly known that a conventional flash A/D is comprised
of a bank of comparators followed by a bank of latches.  The output
of these latches are fed into an encoder to be converted into N bits
digital outputs.  For N bits digital outputs, there are 2**N-1
outputs at the latches.  These outputs form a so-called thermometer
code.  The new encoder takes advantage of the flash A/D physical
layout.  The 2**N-1 comparators and latches are layed out in a 2**N/2
by 2**N/2 matrix.  For illustration, a 6-bit A/D will be considered.
The matrix used will be 8 by 8.  With each of the 8 rows, there are 8
outputs from the latches, as shown in Fig. 1.  The new encoder is
simply made up of a 6 by 8 matrix of the BiCMOS tri-state circuit, as
shown in Fig. 1.  The outputs of all 8 BiCMOS circuits in each column
are connected together so that there are 6 digital final outputs.
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