Browse Prior Art Database

Digital Signal Processors Accelerator Zipping Mode

IP.com Disclosure Number: IPCOM000115823D
Original Publication Date: 1995-Jun-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 156K

Publishing Venue

IBM

Related People

Ho-Lung, MG: AUTHOR [+4]

Abstract

Disclosed is a Digital Signal Processors (DSP) Accelerator Mode of operation to increase the performance of a digital processor system using the DSP Accelerator to allow Filter Zipping with maximum utilization (E=2.00).

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Digital Signal Processors Accelerator Zipping Mode

      Disclosed is a Digital Signal Processors (DSP) Accelerator Mode
of operation to increase the performance of a digital processor
system using the DSP Accelerator to allow Filter Zipping with maximum
utilization (E=2.00).

      This Disclosure describes a new mode for the DSP Accelerator
for real filter Zipping.  In cases where purely real filtering is
done on a sample by sample basis, maximum performance can be achieved
by adding a new mode where instead of selecting IRAM ReadWrite, this
bit selects a register bank (R0/R3 or R4/R7).

      Conventional digital signal processors have three operations in
parallel in a machine cycle that involves a Memory Access, ALU
operation and a Multiply.

      Standard Convolutions are limited by the number of memory
access cycles available.  Prior Art has shown how zipping can be used
to share some computation involved based on fetched data.

      It has been shown how additional memory access and multiply
accumulate can be used to further speed operation of signal
processing algorithms.

      The current invention combines the dual access capability and
zipping to maximize computation power on real time convolution
algorithms that are necessary in high speed subscriber loop receivers
of today.
  Simplex Zipping Mathematica: The following shows two consecutive
filter calculations:
  Y sub k %% = %% sum from SCRIPTL=0 to N of % h sub SCRIPTL
   %% x sub <k-SCRIPTL>
  Y sub k+1 %% = %% sum from SCRIPTL=0 to N of % h sub SCRIPTL
   %% x sub <k-SCRIPTL+1>
  Simplex Zipping Flow: The following shows the flow of operation
for the new mode of operation.  Note RM and RMp are the two
Multiplier
outputs.
  Simplex Zipping Implementation: The Data flow is shown in Fig. 1
SC0p is equal to either SC0 or the compliment of SC0 based on the
current
...