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Joint Test Action Group Error Injection Configuration

IP.com Disclosure Number: IPCOM000115852D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 90K

Publishing Venue

IBM

Related People

Walls, AD: AUTHOR [+2]

Abstract

Joint Test Action Group (JTAG) involves a standard serial interface, for connecting a set of chips, an on chip logical state machine for managing the serial interface (TAP), and a set of on chip boundary scan cells one for each chip driver, receiver, and driver enable. IEEE JTAG BOUNDARY SCAN-CELL satisfies the industry standard objective of being able to force or sense any chip I/O on which it is used. The function is to be able to provide an interconnect test of a multi-chip assembly, with out requiring a fixture or unique test probe device for every product type. JTAG also includes the concept of a Built In Self Test (BIST) in which the Boundary Scan Cells serve as the source or terminus of the chip signal paths during the test sequence.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Joint Test Action Group Error Injection Configuration

      Joint Test Action Group (JTAG) involves a standard serial
interface, for connecting a set of chips, an on chip logical state
machine for managing the serial interface (TAP), and a set of on chip
boundary scan cells one for each chip driver, receiver, and driver
enable.  IEEE JTAG BOUNDARY SCAN-CELL satisfies the industry standard
objective of being able to force or sense any chip I/O on which it is
used.  The function is to be able to provide an interconnect test of
a multi-chip assembly, with out requiring a fixture or unique test
probe device for every product type.  JTAG also includes the concept
of a Built In Self Test (BIST) in which the Boundary Scan Cells serve
as the source or terminus of the chip signal paths during the test
sequence.

      This invention adds to this Boundary Scan Cell definition in a
simple way to allow imposing  a state on a mask selected set of I/O
while the remainder of the I/O are in use by the intended chip
function.  This allows imposing error states on any chip I/O while
the chip is in operation, thus, providing a 'bugging' path through
the JTAG interface.

      The IEEE Boundary Scan Cell definition includes two latches,
and three two way multiplexers as illustrated in Fig. 1.  In normal
functional use, the chip signals are propagated from the D0 input
into the 50 output through the Sel 0 multiplexer, while the remainder
of the cell logic does not interfere with the operation.  The
boundary scan data path is from the I/O input to the 90 output, and
is intended to be orthogonal (non-interfering) to the chip logic
function while in operational mode.  Management of the latch clock
signals (A0, B1, Be, C1, C2) and the multiplexer gate signals (T0,
T1, T2) is done by the on chip state machine (TAP).

      The JTAG concept is that the TAP managed signals are available
to al...