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Metastability Reduction in High-Speed Analog-to-Digital Converters by Alternating Latches

IP.com Disclosure Number: IPCOM000115886D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 96K

Publishing Venue

IBM

Related People

Harr, JD: AUTHOR

Abstract

In high speed Analog-to-Digital converters, the input signal is compared to threshold voltages by comparator circuits. The outputs of these comparator circuits are sampled by latches which are usually polarity-hold type latches (sometimes referred to as D type transparent latches) and often made from cascade current switch circuits. If the input signal is very close to the threshold voltage of one of the comparators, then the corresponding latch can enter a metastable state, which may not be resolved before the next clock, possibly causing an error.

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Metastability Reduction in High-Speed Analog-to-Digital Converters
by Alternating Latches

      In high speed Analog-to-Digital converters, the input signal is
compared to threshold voltages by comparator circuits.  The outputs
of these comparator circuits are sampled by latches which are usually
polarity-hold type latches (sometimes referred to as D type
transparent latches) and often made from cascade current switch
circuits.  If the input signal is very close to the threshold voltage
of one of the comparators, then the corresponding latch can enter a
metastable state, which may not be resolved before the next clock,
possibly causing an error.

      The nature of Polarity-Hold (PH) latches is that during the
positive half clock cycle, the latch output is forced to follow the
input .  At the instant the clock makes a transition from positive to
negative, the input is disconnected from the latch and the last value
of the input is left in the latch.  If this value was close to the
threshold, the latch is left in the metastable state.  Thus, only one
half clock cycle is available in which a metastable PH latch can come
out of metastability and reach a stable state, and the Mean Time
Between Failures (MTBF) is given by
  MTBF = k*exp((tc/2)*(1/tsw))                     (eqn.  1)
where tc/2 is the half clock period  the latch has to come out of
metastability, and (the latch switching time) k are constants fixed
by the latch design.

      To improve the MTBF, two latches are often used in cascade.
The second latch has an MTBF identical to the first latch , and the
combination has an overall MTBF of:
  MTBF= k*exp(tc*(1/tsw))                          (eqn.  2)

      This is much better than for a single latch, because another
half clock cycle is used to come out of metastability.  However, only
two half-cycles are used, out of two full cycles.

      Significant improvement can be made by connecting the latches
in parallel, as shown by Fig. 1.  Switches  S1 and S2 operate at half
the clock frequency...