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Coherency Monitor: System Coherency Protocol Verification Tool

IP.com Disclosure Number: IPCOM000115888D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 147K

Publishing Venue

IBM

Related People

Kreulen, JT: AUTHOR [+5]

Abstract

One of the major tasks in functional verification of cache coherent MultiProcessor (MP) systems, is verification of the cache coherency protocols and access ordering. The traditional method used for verification of a CPU complex (processor, caches, etc.) is to generate a set of instructions which the system under test executes and compare the final simulated result with the expected result for determining whether the system being verified is functioning correctly.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 39% of the total text.

Coherency Monitor:  System Coherency Protocol Verification Tool

      One of the major tasks in functional verification of cache
coherent MultiProcessor (MP) systems, is verification of the cache
coherency protocols and access ordering.  The traditional method used
for verification of a CPU complex (processor, caches, etc.) is to
generate a set of instructions which the system under test executes
and compare the final simulated result with the expected result for
determining whether the system being verified is functioning
correctly.

      In a cache coherent MP system, it is not always possible to
determine the result of the series of instructions in advance (in the
presence of true sharing, and false sharing in some cases).  It is
also possible for the system under test to correctly complete the
testcase (correct final result) but still contain coherency protocol
violations which had not resulted in a wrong final state.  Also, the
order in which instructions complete has to be observed and its
adherence to the storage ordering model (weak or firm) followed by
the system needs to be verified.

      This disclosure presents a tool which had been developed to
solve the problems mentioned above.  The coherency monitor is a tool
which is used to a) verify the operation of the cache coherency
protocols used in the system b) Dynamically check for the correct
data streams flowing in the system c) verify the order by which
instructions complete and check for the system's compliance with the
storage model used.  In addition to that, the coherency monitor
provides a set of diagnostic information which is helpful in tracing
the operation of the system being verified which can significantly
reduce the time it takes to debug a problem encountered during the
verification phase.

      A general MP configuration is depicted in Fig. 1.  As can be
seen, typically one or more first level caches (henceforth L1) are
connected to the second level cache controllers (henceforth L2) which
in turn are connected to the main memory (henceforth L3) via some
interconnect structure (bus, switch or a combination of the two).

      In order to solve the above mentioned problem, a tool was
developed to verify the architecture and implementation of a PowerPC*
based multi-processor system under development.

      The coherency monitor consists of two pieces.  The first piece
monitors the interfaces which exist in the system (for example L1_L2
interface).  This is referred to as "spy element".  The second and
the main piece is the base coherency monitor.  The spy element
provides the coherency monitor the information on all transactions
which take place on the interface being monitored.

      This technique allows the coherency monitor to be independent
of the low level bus protocols used between the different parts of
the system.  Only the pieces which observe the interfaces need to be
aware of the communication protocol implement...