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Browse Prior Art Database

PowerPC Programmable Exception Vectors at the High Address

IP.com Disclosure Number: IPCOM000115896D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Bealkowski, R: AUTHOR [+2]

Abstract

Disclosed is a method and apparatus for enabling programmable exception vectors at the PowerPC(*) high address setting. Enabling programmable exception vectors at the high address setting avoids potential conflicts with hardware bus-master data transfers when the system is running PC-type emulation software.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 64% of the total text.

PowerPC Programmable Exception Vectors at the High Address

      Disclosed is a method and apparatus for enabling programmable
exception vectors at the PowerPC(*)  high address setting.  Enabling
programmable exception vectors at the high address setting avoids
potential conflicts with hardware bus-master data transfers when the
system is running PC-type emulation software.

      The PowerPC family of microprocessors support two locations for
the exception table.  The table may begin at 0x00000000 or
0xFFF00000.  Read-Only Storage (ROS) is in the 0xFFF00000 region.
Random Access Memory (RAM) is in the 0x00000000 region.  The default
setting for the exception table is 0xFFF00000.  Once the computer
system is initialized and the operating system takes control the
exception table location is changed to 0x00000000.  This allows the
operating system to provide the necessary loadable exception
handlers.

      The Figure shows how the system memory map is enhanced to
support a region of RAM starting at the high exception table address
0xFFF00000.  RAM or ROS is placed at 0xFFF00000 with ROS as the
default.  The region of RAM placed at 0xFFF00000 allows the exception
prefix to be set "high"  and allows the exception table to be
programmable.  Under program control the ROS is deactivated and the
RAM activated.  This requires the memory control hardware to be
extended to provide an address register and a control bit.  The
address register specifies the begi...