Browse Prior Art Database

Two-Speed Delay Cell

IP.com Disclosure Number: IPCOM000115909D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Philpott, RA: AUTHOR

Abstract

A two-speed delay cell is disclosed. The two-speed delay cell is use to achieve a relative delay equal to 50% of the nominal delay in each cell.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 72% of the total text.

Two-Speed Delay Cell

      A two-speed delay cell is disclosed.  The two-speed delay cell
is use to achieve a relative delay equal to 50% of the nominal delay
in each cell.

      The two-speed delay cell is used in a programmable delay line
as shown in Fig. 1.  A fixed delay is added after the dummy
multiplexer
and the two-speed delay cell is added after the N:1 multiplexer.
Thus
the difference between the SHIFTED CLOCK and REFERENCE CLOCK signals
is controlled by a coarse and fine adjustment.  The coarse adjustment
is determined by the number of delay cells selected by the N:1
multiplexer.  The fine adjustment is determined by the speed setting
of the two-speed delay cell.

      The two-speed delay cell has a fast and a slow mode.  In fast
mode, its delay is the same as the other delay cells.  In slow mode,
its delay is 50% longer than the other delay cells.  This slow mode
is how a relative step size equal to half the delay of the delay
cells
can be achieved without running the delay cells at twice the speed.

      The circuit schematic for the fixed delay cell used in the
programmable delay line is shown in Fig. 2.  The delay consists of an
NPN differential pair (Q1 and Q2) that have PFETs (T1 and T2)
operating in their linear region for pull-up resistors.  The constant
delay through this cell is maintained by adjusting the bias current
(Ibias) to compensate for parasitic capacitance variations from
processing.  The operational amplifier in t...