Browse Prior Art Database

Multi-Stage Synchronization System with Multiple Frequency Clock

IP.com Disclosure Number: IPCOM000115931D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 83K

Publishing Venue

IBM

Related People

Inazumi, J: AUTHOR

Abstract

Disclosed is a synchronization system which uses a block driven by multiple frequency clock for finer resolution synchronization. Phase offset between higher frequency and base frequency is to be roughly fixed but at any phase. This means gradual drift of phase offset does not cause any error and no adjustment is required.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multi-Stage Synchronization System with Multiple Frequency Clock

      Disclosed is a synchronization system which uses a block driven
by multiple frequency clock for finer resolution synchronization.
Phase offset between higher frequency and base frequency is to be
roughly fixed but at any phase.  This means gradual drift of phase
offset does not cause any error and no adjustment is required.

      Fig. 1 shows an example of this system.  Block.A is driven by
base frequency clock(C1) while block.B is driven by multiple
frequency clock (Cn...cycle time of Cn x n = cycle time of C1) of
base clock.  Both blocks receive sync reference signal.S which is
running in a constant cycle.  Block.A outputs signal.D which is
sync.ed (has almost constant delay) from rising edge of signal.S.
Variance of sync(delay) of signal.D is within cycle time of C1(T0).
Signal.P output from block.A is a detected signal of rising edge of
signal.S.  Fig. 2 shows an example of S, P, D and C1.

      Fig. 3 shows internal blocks of block.B.  B1 detects rising
edge of signal.S and outputs signal.S1.  B2 is a 2n counter which
outputs value.E and is initialized by S1.  B3 detects rising edge of
signal.P and outputs signal.P1.  B4 latches value.E at P1 and outputs
latched value.F.  B5 outputs signal.H and value.G.  Value.G is value
(m-F) while constant.m is selected as (m>2n).  Signal.H is a cycle.n
signal which is output at Eq.1 timing.
  ( E mod n ) = ( ( F + k ) mod n )
  while ( k = 0,1, ..  or n-1,  mod = residual function ) ......
Eq.1

      B6 latches signal.D at signal.H and outputs signal.Dn.  If
value.k is selected appropriately stable D can be captured.  Dn is
also a cycle.n signal (i.e., cycle of C1).  B7 is a shift register of
j stages(j>m) and outputs all stages' output signals as Wj.  B8
selects one of Wj according to value.G. (ex. If G=g, output of
stage.g is selected.) Signal.V...