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Method and Structure to enable use of Flip Chip Bonding with Low-Temperature Solder on Non-Expansion Matched Substrates

IP.com Disclosure Number: IPCOM000115941D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 121K

Publishing Venue

IBM

Related People

Bindra, P: AUTHOR [+6]

Abstract

The highest density of input/output (I/O) connections from a chip to a substrate is achieved with Flip Chip Bonding (C4). The C4 attach method employs an array of small solder bumps on the chip. The large number of input/output (I/O) connections required for a high density chip leads to a fine spacing of the C4 array. The numerous advantages of C4 technologies have been reported elsewhere (1,2). In theory, the number of interconnections achievable with C4 technology has no limit as long as the coefficient of thermal expansion (CTE) of the substrate matches that of the chip. Unfortunately most available substrates have a CTE of about twice that of silicon. It is therefore desirable to have a chip joining method which can tolerate a CTE mismatch between the chip and the substrate.

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This is the abbreviated version, containing approximately 52% of the total text.

Method and Structure to enable use of Flip Chip Bonding with Low-Temperature
Solder on Non-Expansion Matched Substrates

      The highest density of input/output (I/O) connections from a
chip to a substrate is achieved with Flip Chip Bonding (C4).  The C4
attach method employs an array of small solder bumps on the chip.
The large number of input/output (I/O) connections required for a
high density chip leads to a fine spacing of the C4 array.  The
numerous advantages of C4 technologies have been reported elsewhere
(1,2).  In theory, the number of interconnections achievable with C4
technology has no limit as long as the coefficient of thermal
expansion (CTE) of the substrate matches that of the chip.
Unfortunately
most available substrates have a CTE of about twice that of silicon.
It
is therefore desirable to have a chip joining method which can
tolerate
a CTE mismatch between the chip and the substrate.

      The conventional C4 process solves the problem of creep in the
solder bump by using a high lead solder with very low creep.  The
high lead solder also has a high melting point, which with a CTE
mismatch causes a large initial strain in the package as it cools
from the reflow temperature of the high lead solder.  The CTE
mismatch, high processing temperature, and creep problems can be
solved by attaching chips using an array of low temperature solder
columns held in a carrier film.  The solder columns increase the
height of the C4 joint, so reduce the strain in the overall column.
The life of the C4 joint is limited by the strain induced by the CTE
mismatch between the chip and substrate.

      Fig. 1 shows a polyimide film with solder columns arranged in
an I beam pattern for attaching a memory chip to a substrate.  The
solder columns shown are 63/37 lead/tin solder.  Fig. 2 shows the
solder columns attached to a 1 meg memory chip.  The solder columns
are produced by allowing liquid solder to wet to a copper plated hole
in the polyimide carrier film.  The holes can be drilled...