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Output Interface Circuitry for Dual-Port Static Random Access Memory that Employs a Clocked Latch-Type Sense Amplifier

IP.com Disclosure Number: IPCOM000115993D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Oullette, MR: AUTHOR [+2]

Abstract

Static output interface circuits for a dual-port SRAM are described which (1) provide differential bitline to single ended conversion, (2) provide high isolation against reverse coupling from the output latch back into the bitlines, and (3) accommodate growable SRAM architectures.

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This is the abbreviated version, containing approximately 64% of the total text.

Output Interface Circuitry for Dual-Port Static Random Access Memory
that Employs a Clocked Latch-Type Sense Amplifier

      Static output interface circuits for a dual-port SRAM are
described which (1) provide differential bitline to single ended
conversion, (2) provide high isolation against reverse coupling from
the output latch back into the bitlines, and (3) accommodate growable
SRAM architectures.

      The left column of Fig. 1 represents the read path of a bitline
multiplexed SRAM from SRAM cell through the sense amp.  The SRAM cell
is at the top.  Inputs are shown for WordLine control (WL), BitLine
PREcharge (BLPRE), BitLine SELect (BLSEL) and Sense Amp PREcharge
(SAPRE).  At the bottom of the left column, input Sense Amp ENBble
(SAENB) gates the clocked latch-type sense amp.  The complementary
bitline outputs (SABLT and SABLC) continue on to the top of the right
column in Fig. 1.

      At the top of the right column in Fig. 1, inverters I0 and I1
each drive a differential-to-single-ended converter, CNV0 and CNV1.
The converter single-ended outputs DBT and DBC drive the OUTPUT LATCH
through pass gates.  Other pass gates allow for multiple data paths
to the OUTPUT LATCH.

      When the OUTPUT LATCH changes states, substantial transient
signals may be reverse coupled back into DBT and DBC, and then to the
inputs of CNV0 and CNV1.  The instantaneous polarity of the reverse
coupled transient signals is dependent on the polarity of the data
that...