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Reduction Method of Radiated Emission from I/F Cable by Data Polarity Control

IP.com Disclosure Number: IPCOM000115998D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Fukuda, K: AUTHOR [+2]

Abstract

Disclosed is a parallel data interface circuit to reduce significant electromagnetic radiation when all or major part of the interface signals have strong high frequency component by repeating the same signal pattern. Fig. 1 shows a typical interface signal for such case, where the 4-bit wide data is transferred with the sample clock, CLK. The data is expected to be sampled at rising edge of CLK. Therefore the figure shows the transmission of data '0100101001' for every 4 bits.

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Reduction Method of Radiated Emission from I/F Cable by Data Polarity
Control

      Disclosed is a parallel data interface circuit to reduce
significant electromagnetic radiation when all or major part of the
interface signals have strong high frequency component by repeating
the same signal pattern.  Fig. 1 shows a typical interface signal for
such case, where the 4-bit wide data is transferred with the sample
clock, CLK.  The data is expected to be sampled at rising edge of
CLK.  Therefore the figure shows the transmission of data
'0100101001'
for every 4 bits.

      The EMI radiation from two trains of the same data can be
reduced by detecting the repetition of signal train and changing the
signal polarity of the repeated signal train.  In Fig. 1, the signal
train of '01001' is repeated.  The signal repetition time is T0 or
Repetitive Rate is 1/T0.  Fig. 2 shows the result of polarity change.
The signal repetition time is doubled compared to Fig. 1.  The signal
repetition time is now 2T0 and Repetitive Rate is 1/(2T0), that is
the basic frequency is reduced to half of that in Fig. 1.

      An example of implementation of above signal transformation is
shown in Fig. 3.  The circuit is comparing data pattern of 4 sample
clock time with that for next 4 sample clock period.  The 4 line-wide
bus is assumed.

      Data Memory Logic (1) consists of four 8-bit shift registers.
The data in each line is shifted in each shift register respectively.
The output signal 'SHIFT(i,j)' represents j'th shifted data of data
line i.

  ...