Browse Prior Art Database

Test Friendly Scheme for Read Only Storage

IP.com Disclosure Number: IPCOM000116003D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 118K

Publishing Venue

IBM

Related People

Bredin, F: AUTHOR [+2]

Abstract

Read Only Storage (ROS) Test Friendly Scheme description - Up to now, testing Read Only Storage embedded macros was driven by the tester environment, the amount of tester pins and the fashionable method which was grown up in different areas.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Test Friendly Scheme for Read Only Storage

      Read Only Storage (ROS) Test Friendly Scheme description - Up
to now, testing Read Only Storage embedded macros was driven by the
tester environment, the amount of tester pins and the fashionable
method which was grown up in different areas.

      Today, in order to fit with the RAM test method, the trend is
to closely include to the ROS macro, an additive combinatory logic.
Then some test patterns are applied through some scannable latches
and multiplexers to check the macro functionality.  This solution,
named ABIST is good and may fill the bill in many cases.
Unfortunately,
it seems to by-pass silicon area saving options and is not really
adapted
in case growable or modular ROS macros are required.

      The solution, beyond the well-known old method, using TROS and
MTR, is the disclosed solution which:
  1.  saves about 30% of the ROS silicon active area by removing
ABIST
       and its associated logic from the design.
  2.  improves electrical performance by removing multiplexer circuit
       from address paths.
  3.  fills the bill in other embedded macros where microcode is
       included such as EEPROM.
  4.  suits for new ROS family (CMOS5-Phoenix) which are likely to
need
       "Test Scheme" in the near future.

      Actual ROS modelization methods - As shown in Fig. 1, two old
ROS modelization schemes for test generation are described either in
CMOS2 or in CMOS4 methodologies.

      In CMOS2, the ROS is embedded into a chip and the test is
performed throught some Primary Input (PI), Primary Output (PO) or
scan latches (SRL).  This method is essentially based on APG/MTR
processing.  The MTR is manually defined and represents the ROS test
sequence.

      In CMOS4, the scheme is roughly equivalent to CMOS2 methodology
but the ROS macro is surrounded by one ABIST logic.  This ABIST logic
is connected to PI/PO of the chip and through some scan latches.  The
ABIST is then activated by a MTR.  The test sequence is manually
defined in the ABIST hardware.  The CMOS4 MTR is smaller than the
CMOS2 MTR and it is also manually defined.

   ...