Browse Prior Art Database

Parallel Processing during Flash Busy Operations

IP.com Disclosure Number: IPCOM000116005D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Ho, W: AUTHOR [+4]

Abstract

Disclosed is a method to allow other attached devices to perform their functions when Flash or EEPROM devices are busy doing the Write or Erase function.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Parallel Processing during Flash Busy Operations

      Disclosed is a method to allow other attached devices to
perform their functions when Flash or EEPROM devices are busy doing
the Write or Erase function.

      Typical Flash and EEPROM type of storage devices become busy
during the period of time that the device is actually erasing or
writing its memory component.  Many systems which use these devices
tie up the attached interface during this busy period of time.  No
operations targeted to other devices attached to this interface can
occur during this time.

      When an Erase or Write operation is initiated to the Flash or
EEPROM device, a status Busy (B) latch, indicating the Flash/EEPROM
is busy, is set.  Control is then disconnected from the bus and other
operations on the interface bus are allowed to take place.  The
Flash/EEPROM busy signal is monitored to know when the Erase or Write
operation is complete.  The (B) Busy status latch is reset when the
Flash/EEPROM operation is complete.  If during the time that the Busy
(B) latch is on another operation on that bus is targeted for the
Flash/EEPROM, the added logic must inhibit that operation from taking
place until the Busy latch is Reset.