Browse Prior Art Database

Dirty Cache Data Detection

IP.com Disclosure Number: IPCOM000116047D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Fujita, N: AUTHOR [+2]

Abstract

Disclosed is a write-back cache system implementation. By providing the status bit which describes data is dirty or not for every bus size data, the snoop hit ratio is reduced and can implement write back cache system easily.

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This is the abbreviated version, containing approximately 100% of the total text.

Dirty Cache Data Detection

      Disclosed is a write-back cache system implementation.  By
providing the status bit which describes data is dirty or not for
every bus size data, the snoop hit ratio is reduced and can implement
write back cache system easily.

      The Figure shows the example of this cache system where  the
cache line size is 16byte and the cache bus size is 4 byte.  The
cache data status bit is provided every 4byte data (bus size).  When
it become necessary to write back the dirty data, the cache system
write back only this 4 byte data to main memory.

       Using this method, (1) snoop hit ratio is reduced, (2)
write-back time will be shorter, and (3) memory controller does not
care about continuous write cycle even for write back cache system.

       This may be implemented into the L1 cache inside a processor,
because it's no need for the memory controller which faces to the
processor to modify.