Browse Prior Art Database

Synchronous Output Enable Delay for CMOS Memory

IP.com Disclosure Number: IPCOM000116054D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Rossi, RD: AUTHOR

Abstract

A technique is described for a RAM semiconductor chip that minimizes the time when the RAM actively controls a common I/O bus. As a result, the I/O bus is available without contention for use by peripheral chips over the maximum possible time.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 80% of the total text.

Synchronous Output Enable Delay for CMOS Memory

      A technique is described for a RAM semiconductor chip that
minimizes the time when the RAM actively controls a common I/O bus.
As a result, the I/O bus is available without contention for use by
peripheral chips over the maximum possible time.

      In the Figure, the DELAY signal is chosen to coincide with the
internal array data that is presented to the RAM I/O bus driver.
DELAY is derived from a dummy word line so that it tracks with array
access timing across variations in semiconductor process and applied
conditions.  The DELAY signal is normally high.  READ and WRITE are
normally low.  Input Chip Select Internal (CSI) is latched prior to
the circuits shown.  Input Output Enable (OE) is driven external to
the RAM chip.

      If CSI is low (chip not selected), and DELAY is high, latch
I2/I5 is reset, and the INTernal Output Enable (INTOE) goes high so
that the I/O bus driver assumes its high-Z state.  The WRITE mode
causes a similar condition.  Immediately after a high WRITE pulse
occurs and DELAY is high, latch I6/I7 is reset, INTOE goes high, and
the I/O bus driver is driven to its high-Z state.

      When the READ signal goes high, latch I0/I1 is set immediately,
but latch I6/I7 is not set until DELAY goes low.  The derivation of
the DELAY signal assures that the I/O bus driver comes out of its
high-Z state synchronously, but with the shortest possible delay
consistent with valid data at...