Browse Prior Art Database

Cycle Extension for Write Completion

IP.com Disclosure Number: IPCOM000116062D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Kirihata, T: AUTHOR [+2]

Abstract

Devices such as decoding isolators are often used between the bit switch/sense amplifier and the bit line of semiconductor memory chips. These devices may introduce delay in the write operation. A method is described below which extends the active cycle into restore time to allow more time to complete the write operation.

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This is the abbreviated version, containing approximately 80% of the total text.

Cycle Extension for Write Completion

      Devices such as decoding isolators are often used between the
bit switch/sense amplifier and the bit line of semiconductor memory
chips.  These devices may introduce delay in the write operation.  A
method is described below which extends the active cycle into restore
time to allow more time to complete the write operation.

      When the write operation occurs early in the active cycle, the
conventional RAS signal (XRASN as shown in Fig. 1) passes through the
RAS RECEIVER to appear unmodified as output RASN.  If the write
operation occurs later in the active cycle, just prior to RAS
restore, it is desirable to extend the active cycle to allow more
time to complete the write operation.  In Fig. 2, the leading edge of
each internal write pulse initiates a one-shot (KWG0-KWG5), and the
one-shot outputs are combined and stretched to generate a single
RASDN signal.  Because of skew between internal write pulses, the
leading edge of the write pulse that occurs last defines the
beginning of RASDN by means of the circuits shown in Fig. 2.  The
delay between the leading edge of the last internal write pulse and
the end of RASDN is shown in Fig. 3.

      When the write operation occurs near the end of the normal
active cycle, RASDN is used in Fig. 1 to stretch RASN wide enough to
guarantee sufficient write time.  When RAS rises, the input logic
shuts down the column address system and the data path.  Trwl and
Tcwl spec...