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Browse Prior Art Database

Complimentary Memory Hierarchies

IP.com Disclosure Number: IPCOM000116077D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

So, K: AUTHOR

Abstract

In a conventional computer system with multiple levels of caches, say L1 (level-one) and L2 (level-two) caches, where L1 is closer to the CPU, if a memory access to a memory location misses both L1 and L2, a line, say l, containing the location will be loaded from memory to both caches. But because of reference locality, the CPU only uses line l in L1 and line l in L2 is not used until the copy in L1 is replaced. This arrangement not only wastes the capacity of L2 cache, it also wastes L2 bandwidth for re-load and may delay any miss if L2 has to be re-loaded before sending any missing line to L1 and the CPU.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 80% of the total text.

Complimentary Memory Hierarchies

      In a conventional computer system with multiple levels of
caches, say L1 (level-one) and L2 (level-two) caches, where L1 is
closer to the CPU, if a memory access to a memory location misses
both L1 and L2, a line, say l, containing the location will be loaded
from memory to both caches.  But because of reference locality, the
CPU only uses line l in L1 and line l in L2 is not used until the
copy in L1 is replaced.  This arrangement not only wastes the
capacity of L2 cache, it also wastes L2 bandwidth for re-load and may
delay any miss if L2 has to be re-loaded before sending any missing
line to L1 and the CPU.

      Disclosed is a complimentary memory hierarchy such that the L2
re-load can be avoided for better performance.  Assume that L1 is a
store-in cache a d a memory access is represented by an access to
line l.  The memory hierarchy is operated in the following ways:
  o  A memory access to line l is completed if line l is in L1.
  o  If line l is not in L1, the access is sent to search against L2
      cache.  If line 1 is found in L2, it is loaded to L1 and the L1
      line replaced by line l is stored back to L2.
  o  If the memory access to line l misses both L1 and L2 caches.
Line
      l is loaded from the memory directly to L1.  Line l is not
loaded
      to L2.  Again, the line replaced from L1 is stored back to L2.

      If the memory hierarchy is an MP system, then a remot...