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Browse Prior Art Database

Full Bit Prefetch

IP.com Disclosure Number: IPCOM000116078D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Hosokawa, K: AUTHOR [+2]

Abstract

Disclosed is a circuit for synchronous DRAM data path which allows next RAS and CAS accesses during burst read of the previous data, resulting into a seamless read operation for any row addresses.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Full Bit Prefetch

      Disclosed is a circuit for synchronous DRAM data path which
allows next RAS and CAS accesses during burst read of the previous
data, resulting into a seamless read operation for any row addresses.

      Fig. 1 shows a data path block diagram.  This data path design
is based on a full bit prefetch architecture which latches the same
numbers of data as the burst length (up to eight bits) in I/O sense
amplifier by a single CAS read access.  One of eight data in I/O
sense amplifier which correspond to the first column address is
connected to a read buffer.  The sequence control circuit makes a
parallel to serial transfer on latched eight bit data.  Since the
full burst read data are transferred to I/O sense amplifier before
the second clock, it is not necessary to keep the selected word line
active after this clock.  So the precharge operation can start as
early as two clocks before the read data out.  Fig. 2 shows RAS and
CAS access timing chart.  The restore operation can be hidden during
the data burst read.  It means that a seamless read operation is
possible for any row address even within the same bank.

      This full bit prefetch architecture enhances functions and
performance of a synchronous DRAM applications.