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Computer Memory Testing using an Operational Test

IP.com Disclosure Number: IPCOM000116081D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Sarkany, EF: AUTHOR

Abstract

Disclosed is an operational memory test designed to check for gross functional defects in memory chips. It also verifies that there is proper address decoding within the chip. The signal timings to the memory array are relaxed from the specified limits of the chip during this test.

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Computer Memory Testing using an Operational Test

      Disclosed is an operational memory test designed to check for
gross functional defects in memory chips.  It also verifies that
there is proper address decoding within the chip.  The signal timings
to the memory array are relaxed from the specified limits of the chip
during this test.

The test is performed in four steps:
  o  Step 1: Load the array with all zeroes in every address.
  o  Step 2: Starting at the first address, read the zeroes, write
all
      ones, read the ones, and rewrite the ones.  Then, increment the
      address and repeat.
  o  Step 3: Starting again at the first address, read the ones
      written in the previous step, write all zeroes, read the
zeroes,
      and write all ones.  Then, increment the address and repeat.
  o  Step 4: Starting at the last address, read the ones written in
      the previous step, write all zeroes, read the zeroes, and
rewrite
      the zeroes.  Then, decrement the address and repeat.

Then the test is repeated using the complementary data.