Browse Prior Art Database

Reducing Random Logic Macros Clock Skew in the VLSI Interactive Design Automation System Tool Methodology

IP.com Disclosure Number: IPCOM000116086D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Fentanes, J: AUTHOR [+3]

Abstract

Random Logic Macros (RLM) in the VLSI Interactive Design Automation System (VIDAS) create special clock wiring problems. Higher cycle times allowed chip clock skew to be much higher so the RLM clock skew could be ignored.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 76% of the total text.

Reducing Random Logic Macros Clock Skew in the VLSI Interactive Design
Automation System Tool Methodology

      Random Logic Macros (RLM) in the VLSI Interactive Design
Automation System (VIDAS) create special clock wiring problems.
Higher cycle times allowed chip clock skew to be much higher so the
RLM clock skew could be ignored.

      The VIDAS wiring program would daisychain the clock wire
through the RLM.  The last checkpoint would be much later than the
first checkpoint because of RC delays.  The high skew between the
clockpoints is unacceptable when a fast clock is used.

      The Virtual In-Core Model is modified to create a uniquely
named net name for each clockpoint in the RLM.  Unique net names
force the wiring tool to connect each clockpoint to the main
clocktree without daisychaining.  The removal of daisychaining allows
for a reduced RLM clock skew.
  Step 1: Parsed VIM determines the number of clockpoints in a RLM.
The original global clock net is propagated down to the RLM as a
prewire.  The original prewire will be appended by a number that will
give the prewire uniqueness.  If there were 50 clockpoints and the
original prewire name is CK1_CLKG then the new unique prewires and
clockpoint names would be CK1_CLKG0, CK1_CLKG1, CK1_CLKG2, ....,
CK1_CLKG49.  The new prewires will be at the same location
overlapping each other.
  Step 2: The VIDAS wiring program is forced to individually wire
each
clockpoint to its respective prewire instea...