Browse Prior Art Database

Fast Clock Gating Circuit

IP.com Disclosure Number: IPCOM000116088D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Anderson, P: AUTHOR [+4]

Abstract

Disclosed is a fast clock gating circuit which prevents hold-time problems.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 79% of the total text.

Fast Clock Gating Circuit

      Disclosed is a fast clock gating circuit which prevents
hold-time problems.

      The output stage of the clock gating circuit is sourced by the
clock and the output node is pulled down by the controlling
complementary clock as shown in Fig. 1.  This speeds up the turnoff
time of the gated clock in order to prevent a hold time problem.
Because clock gating is completed at the beginning of the stage, the
setup time of gating data, as it applies to the clock, does not
increase in direct proportion to any delay caused at clock gating.

      When clock gating is implemented as shown in Fig. 2, the rise
delay and the fall delay of the AND gate skews the gated clock from
the master clock.  If the skew becomes large enough to set off the
triggering delay of latch_2, violating the hold-time requirement of
latch_1, the circuit fails.  This is likely to happen when the
capacitance load of the gated clock becomes too large and requires
additional buffering at the AND gate.  This can be corrected by using
the "early" clock to compensate for the skew caused at the clock
gate.  This stresses the setup requirement of gating "data", because
clock gating introduces a "half-cycle path", which makes the setup
requirement difficult to achieve.

      Using the disclosed circuit (Fig. 1), the fall delay from the
master clock to the gated clock is no more than the delay of the pass
gate (T5), which is small enough to prevent holdtime violati...