Browse Prior Art Database

Delayed Instruction Exception Handling

IP.com Disclosure Number: IPCOM000116089D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Golla, RT: AUTHOR [+2]

Abstract

Disclosed is a mechanism by which instruction exceptions can be handled in a delayed manner. Instruction exceptions are normally handled in the same cycle that instructions are fetched from the instruction cache. The system at hand will consist of: an instruction cache (ICACHE), an Effective Address Register (EAR), a translation mechanism (XLATE), Instruction Buffers (IB) and Instruction Buffer Control Logic (IBCL) as shown in Fig. 1.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Delayed Instruction Exception Handling

      Disclosed is a mechanism by which instruction exceptions can be
handled in a delayed manner.  Instruction exceptions are normally
handled in the same cycle that instructions are fetched from the
instruction cache.  The system at hand will consist of: an
instruction cache (ICACHE), an Effective Address Register (EAR), a
translation mechanism (XLATE), Instruction Buffers (IB) and
Instruction Buffer Control Logic (IBCL) as shown in Fig. 1.

      Each cycle the EAR contains the current instruction address
(Fig. 1).  Portions of this address are sent to the ICACHE and the
XLATE unit each cycle.  The XLATE unit uses the address to verify
that the current address can be translated and that the translation
is valid according to the processor architecture.  In an actual
processor, the XLATE unit would consist of one or more of the
following: Translation Look-aside Buffers (TLBs), segment registers
and Block Address Tables (BATs).  If the current address translation
cannot be generated or it is not valid, an instruction exception is
generated.  Typically, this exception is used by the IBCL to prevent
the loading of instructions from the ICACHE into the IB.
Unfortunately,
the generation of the exception by the XLATE unit does not occur
until
late in the processor cycle.  Using this instruction exception to
prevent
fetching of instructions from the ICACH E into the IB can limit the
cycle
time of the processor itself.

      A delayed inst...