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Input/Output Test Circuit

IP.com Disclosure Number: IPCOM000116098D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 133K

Publishing Venue

IBM

Related People

Taylor, JB: AUTHOR

Abstract

Disclosed is the use of an implicitly-addressed I/O test circuit to test and verify the functions of a DMA (Direct Memory Access) controller chip and a Micro Channel* interface chip connected to the test circuit through a bypass bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Input/Output Test Circuit

      Disclosed is the use of an implicitly-addressed I/O test
circuit to test and verify the functions of a DMA (Direct Memory
Access) controller chip and a Micro Channel* interface chip connected
to the test circuit through a bypass bus.

      Fig. 1 is a block diagram showing the DMA controller chip 1 and
the Micro Channel interface chip 2, together with the test circuit,
implemented on a circuit card to be plugged into the Micro Channel
bus 3.  The test circuit consists of an "INIT" (22V10) PLD 4
(Programmable Logic Device), a "CNTRL" PLD 5, a pair of (2Kx9) FIFO
(First In, First Out) buffers 6, a D-latch 7, and a processor 8,
which may be, for example, an 80376 type.  The PLDs interface with
processor 8, initializing FIFO buffers 6 and performing the correct
DMA handshaking to transfer data in either a burst or sequential
mode.  The FIFO buffers 6 receive and transmit up to 2K 16-bit words
at 20 MHZ (megahertz).  The DMA controller chip 1 and Micro Channel
interface chip 2 are connected to the test circuit through a bypass
bus 9.

      The "INIT" PLD 4, which is used to gather specific information
about the desired data transfer, is accessed with a predetermined
address to start the data flow.  This access is accomplished by
performing a write (WR) cycle to I/O address '0001'b (bits A15-A12).
During this write cycle, data bits D0 and D1 are set to perform a
write, with D0=0, or a read (RD), with D0=1, from or to FIFO buffers
3.  Also, the mode of transfer is latched by setting the D1 data bit
to '0' for a burst mode or to '1' for a sequential mode.

      Fig. 2 is a diagram of an "INIT" state machine, triggered off a
rising clock edge, with which the "INIT" PLD performs initializing
operations.  This state machine remains in state 0 until it has been
properly addressed, with ADS#, M/IO#, and WR# signals active.  The
"INIT" state machine then goes to state 1, allowing time for DO and
D1 to settle.  By the next clock edge, the state machine goes to
state 2, in which DO indicates if the FIFO buffers will perform a
read or write cycle, and in which D1 is latched.  After the type of
cycle is determined in this way, the "INT" PLD returns to state 0,
waiting to be addressed again.  The next time the "INIT" PLD is
addressed, the state machine goes to state 3, in which the STOP
command, '0010'b, is issued to the "CNTRL" PLD.

      Referring again to Fig. 1, after being set up for either a read
or write sequence, according to the D0 and D1 outputs provided by the
"INIT" PLD 4, the "CNTRL" PLD 5 issues a DMA_REQ signal.  When a
DMA_ACK signal is received in response, the transmitted data is
stored, and "CNTRL" PLD 2 responds with a DMA_RDY signal.  If the
"CNTRL" PLD 5 has been programmed, with D1=1, DMA_REQ is subsequently
de-asserted; otherwise DMA_REQ remains asserted during the entire
cycle, until the FIFO buffers 6 are full or empty, or...