Browse Prior Art Database

Fully Reprogrammable Fault-Tolerant FLASH Memory System

IP.com Disclosure Number: IPCOM000116103D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 140K

Publishing Venue

IBM

Related People

Kirk, CR: AUTHOR [+2]

Abstract

In today's computers, POST/BIOS code is typically stored in FEPROMs. The FEPROMs allow this code to be updated in a system without hardware changes as was required prior to the availability of FEPROMs. The ability of the host computer to update this code also, unfortunately, creates a significantly negative side effect. If an error occurs during the update, the computer's Power On Self Test (POST) could be corrupted and the computer rendered useless.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 49% of the total text.

Fully Reprogrammable Fault-Tolerant FLASH Memory System

      In today's computers, POST/BIOS code is typically stored in
FEPROMs.  The FEPROMs allow this code to be updated in a system
without hardware changes as was required prior to the availability of
FEPROMs.  The ability of the host computer to update this code also,
unfortunately, creates a significantly negative side effect.  If an
error occurs during the update, the computer's Power On Self Test
(POST) could be corrupted and the computer rendered useless.

      Many methods and products have been devised to eliminate this
problem.  One of the products developed by Intel Corporation was a
FLASH memory device, called the Boot Block device.  This device was
partitioned into several blocks such that all of the blocks were
reprogrammable with the exception of a single, small block called the
boot block.  The idea here was to similarly partition the microcode
such that only the minimal microcode required to reprogram the
alterable partitions was stored in the boot block.  This microcode
will hereafter be referred to as the critical code.  As a result, if
an error occurred during the reprogramming of the alterable
partitions, the boot block partition would be left unaltered and
could thus be used to reprogram again the corrupted partitions.
However, this device presented yet another problem by eliminating the
ability to alter ALL of the microcode.  Since the microcode in the
boot block partition could not be altered by the computer, changing
this microcode would be at least as difficult as changing microcode
stored in an OTP ROM.

      Others vendors have also attempted to solve this problem by
partitioning the FLASH device.  AMD offers a FLASH device which
contains several equal-sized partitions.  This device differs from
the Intel device in that the blocks used to store the critical code
are actually FLASH blocks themselves which can be write protected.
Other vendors such as Texas Instruments and Mitsubishi also offer
FLASH devices which are partitioned into several equal-sized blocks.

      To date, there are not any devices that will solve all of the
problems listed above.  Specifically, no devices exist that will
store microcode in such a fashion that ALL of the code can be updated
by the host computer while also allowing critical code to be
maintained.  Such a device would provide the host computer with the
flexibility to update its own microcode while also providing a
mechanism by which faults occurring during code changes could be
tolerated by the host computer.  The following solution describes
such a device.

New FLASH Architecture - The problem described above is easily
solvable incorporating a nonvolatile paging mechanism into the FLASH
module.  By partitioning the FLASH device into two blocks and
allowing the block locations to be interchanged via paging, either of
the two blocks can be used as the boot block.  This enables the
device to be fu...