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Analyzing Resistance/Capacitance Values without a Timing Run

IP.com Disclosure Number: IPCOM000116116D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Fentanes, J: AUTHOR [+3]

Abstract

Previously, chip integrators waited until a timing run with their RC data completed to analyze the RC problems.

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This is the abbreviated version, containing approximately 68% of the total text.

Analyzing Resistance/Capacitance Values without a Timing Run

      Previously, chip integrators waited until a timing run with
their RC data completed to analyze the RC problems.

      Timing runs on larger chips can take up to an hour to run.  An
alternative approach to analyze RC is to use the RC file.  Usually,
the RC file has nets cluttering up the file that will eventually be
ignored in the timing tool.  The ignored nets make it difficult to
find the real RC problem nets.

      The RC estimator program uses a file to stamp nets a certain RC
value.  The creation of the stamp file presented a problem because
identifying nets manually was too time consuming.  The new program
rcstamp used the timing database to analyze the ignored nets and
stamp them with an RC value of 0.  Rcstamp can also stamp clock nets
and primary input/output until the necessary physical design programs
can be run to accurately models the true wiring of the clock and io.
  o  Step 1: Rcstamp load in the timing database to find the ignored
      nets, clock nets, and primary input and output nets.  Once all
      nets are determined, rcstamp created the stamp file that sets
the
      nets to 0.
  o  Step 2: The chip integrator inputs the stamp file to the RC
      estimator program to get output that is free from ignored nets,
      clock nets, and primary input and output nets.  The chip
      integrator can continue to use the rcstamp file to
i...