Browse Prior Art Database

Clock-Skew Compensation Mechanism for Large Scale Integration

IP.com Disclosure Number: IPCOM000116127D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 86K

Publishing Venue

IBM

Related People

Suminaga, S: AUTHOR

Abstract

Disclosed is a mechanism which minimizes clock-skew with a Programmable Clock-Distribution-Macro. The Clock-Distribution-Macro has driver circuit arrays and delay devices which can be combined or arranged according to the conditions so that all the propagation delays from the clock source to the destination are balanced.

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This is the abbreviated version, containing approximately 59% of the total text.

Clock-Skew Compensation Mechanism for Large Scale Integration

      Disclosed is a mechanism which minimizes clock-skew with a
Programmable Clock-Distribution-Macro.  The Clock-Distribution-Macro
has driver circuit arrays and delay devices which can be combined or
arranged according to the conditions so that all the propagation
delays from the clock source to the destination are balanced.

      Fig. 1 shows the conception of the Clock-Distribution-Macro.
The macro has a certain number of driver circuits (2), and a rule
table which specifies the propagation delays from the input terminal
(1) to the output terminals (4) and slew time of the output clock
signals for considerable combinations of drivers and load conditions
of the output terminals (4) and the resistance capacitance delay for
each wiring between output terminals to the destination.  The driver
circuits (2) are constituted from sub-drivers and may have delay
devices in it.  Each driver circuit (2) may have same drive
capability or different drive capability each other.  According to
the conditions of chip layout, the drivers are combined by automatic
or manual routing (3) with a certain wiring resources referring to
the rule table in order to minimize the skew, propagation delay and
slew time.

      Fig. 2 shows a clock distribution system as an application of
this mechanism.  Block-1 (1), Block-2 (2), Block-3 (3), Block-4 (4),
are hierarchical software blocks, and Block-5 (5), Block-5 (6), RAM
...