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Universal Asynchronous Receiver-Transmitter Chip with Switchable Clock Rate

IP.com Disclosure Number: IPCOM000116148D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Harrison, H: AUTHOR

Abstract

Disclosed is method for operating a Universal Asynchronous Receiver-Transmitter (UART) chip at a first clock frequency for handling relatively low serial data rates and at one or more higher frequencies for handling relatively high serial data rates. While the standard UART clock rate of 1.8432 MHz (megahertz) provides the best support for standard data rates, such as 300, 1200, and 9600 baud, about 38.4 kbaud (kilobaud) is the highest rate which can be comfortably supported at this clock rate. Thus, this clock frequency does not allow the use of higher data rates, particularly in the range of 56 kbaud to 512 kbaud.

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Universal Asynchronous Receiver-Transmitter Chip with Switchable
Clock Rate

      Disclosed is method for operating a Universal Asynchronous
Receiver-Transmitter (UART) chip at a first clock frequency for
handling relatively low serial data rates and at one or more higher
frequencies for handling relatively high serial data rates.  While
the standard UART clock rate of 1.8432 MHz (megahertz) provides the
best support for standard data rates, such as 300, 1200, and 9600
baud, about 38.4 kbaud (kilobaud) is the highest rate which can be
comfortably supported at this clock rate.  Thus, this clock frequency
does not allow the use of higher data rates, particularly in the
range of 56 kbaud to 512 kbaud.

      In the implementation of this method, the highest baud rate
accurately supported at the standard UART frequency, such as 38.4
kbaud at 1.8432 MHz, is first determined.  Next, the clock frequency
which provides the greatest accuracy for the highest baud rate
supported by the hardware is determined.  For example, for a
conventional implementation, this frequency is 8 MHz.  In the system,
the Basic Input/Output System (BIOS) level code is provided with a
capability to recognize the baud rate requested by a user.  This code
is also provided with a capability for manipulating the UART directly
to make clock frequency changes.  Preferably, a data structure is
provided which remembers the last frequency at which the clock rate
of the UART was set, eliminating a nee...