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Modified Cache Line Advance-Replacement Indicator

IP.com Disclosure Number: IPCOM000116161D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 284K

Publishing Venue

IBM

Related People

Haig, RB: AUTHOR [+4]

Abstract

Disclosed is a method and circuit for facilitating the decision process involved in the use of a Secondary Cache, as with the use of a Look-Aside Store in Cache Controller (LASICC). This method allows the Memory Controller either to continue with a processor-initiated read operation or to discontinue the processor read operation because the Second Level Cache is going to initiate a cache write-back first. The circuit for performing this method, a Modified Cache Line Advance Replacement Indicator (MCLARI), uses a set of processor signal pins to decode a cycle, determines if a cache line has been modified, and then drives the CHITM# signal to initiate the write-back sequence.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 22% of the total text.

Modified Cache Line Advance-Replacement Indicator

      Disclosed is a method and circuit for facilitating the decision
process involved in the use of a Secondary Cache, as with the use of
a Look-Aside Store in Cache Controller (LASICC).  This method allows
the Memory Controller either to continue with a processor-initiated
read operation or to discontinue the processor read operation because
the Second Level Cache is going to initiate a cache write-back first.
The circuit for performing this method, a Modified Cache Line Advance
Replacement Indicator (MCLARI), uses a set of processor signal pins
to decode a cycle, determines if a cache line has been modified, and
then drives the CHITM# signal to initiate the write-back sequence.

      Fig. 1 is a block diagram schematically showing a typical use
of a MCLARI in a system.  The Central Processing Unit (CPU) complex 1
includes a first level CPU cache 2.  A data bus 3 connects CPU
complex 1 with a memory controller 4, with a an external cache 5 and
with conventional system memory 6, having slow read and write access
times compared to the cache memories.  Cache 5 includes a LASICC 7
and the MCLARI 8, which is connected to memory controller 4.  Cache 5
is a complete secondary cache subsystem, offering write-back and
write-through operation supported on a line by line basis in the
cache.  The cache is designed to supply data to CPU complex 1 in a
zero wait state for a cache read hit, and it can accept data from the
CPU in a zero wait state for write cycles that hit a write-back cache
line.  To facilitate an understanding of the operation of the system,
a description of several signals will now be provided.

      First, the Memory Start signal, START#, is directed as an
output of MCLARI 7 to memory controller 4 to indicate, when low
(active), that the memory controller should handle the current memory
cycle.  This signal is driven high (inactive) on all I/O and special
cycles which must be handled by the memory controller.  This signal
is driven active in T1 cycles, with ADS#, for all second-level cache
replacement, snoop, and flush write-back cycles.  This signal is
driven active during the first T2 cycle on CPU cycles which the
memory controller must handle.  This signal is driven inactive when
the cache samples the SBOFF# signal at a low (active) level.  START#
is driven active on memory write cycles when ADS# and EADS# are
active simultaneously and when the cache line is set to a
write-through mode.

      The Cache Hit Modified signal, CHITM#, provided as an output of
MCLARI 8, is driven active (low) by the cache one clock after EADS#
is active, indicating a dirty line at the snoop address.  If a dirty
line is hit, the cache performs a write-back operation after gaining
control of the local bus by driving CBOFF#, unless HITM# from the CPU
complex 1 is active.  If HITM# is active, the CPU complex is presumed
to have the most current data, so the write-back operati...