Browse Prior Art Database

Creating Sector Clocks from One Global Clock in the VLSI Interactive Design Automation System Database

IP.com Disclosure Number: IPCOM000116170D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Fentanes, J: AUTHOR [+2]

Abstract

A program is disclosed that divides a chip into a number of sectors and assigns a sector clock to all macros in that area.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 86% of the total text.

Creating Sector Clocks from One Global Clock in the VLSI Interactive
Design Automation System Database

      A program is disclosed that divides a chip into a number of
sectors and assigns a sector clock to all macros in that area.

      Virtual In-core Model (VIM) test editing provides the easiest
way to create the new sector clocks and assign them based on which
sector the clockpoint was located for a given macro.  Quadclk is the
introduced tool that will divide a chip into a number of sectors,
create new clocks, and assign the new sector clocks to the macros in
their given sector area.
  Step 1: Quadclk as a default divides the chip into four sectors and
as clock name to each sector.  The global clock is CK0_CLKGP.  The
new sector names are CK0_CLKGP0, CK0_CLKGP1, CK0_CLKGP2, and
CK0_CLKGP3.
  Step 2: The VIM is read determining which macro's clockpoints
are located in a given sector.  Once the sector is determined for a
macro its clock input is changed from the global name, CK0_CLKGP, to
the sector name, CK0_CLKGP#.  (# = 0,1,2,3)
  Step 3: The wire length from the starting point of the sector
clock to the macro clockpoint is made to determine that the maximum
clock wire length is not exceeded.  If the maximum is exceeded, then
the number of sectors has to be increased until the desired clock
wire length is achieved.

      Quadclk provides an easy way for the chip integrator to divide
the clock into sectors without requiring the logic designers to...