Browse Prior Art Database

ASCII Representation of Virtual In-Core Model Partitioned Stack

IP.com Disclosure Number: IPCOM000116173D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Fentanes, J: AUTHOR [+3]

Abstract

Chip integrators produce a initial floor plan from all the available virtual In-Core Model (VIM) data in the VLSI Interactive Design Automation System (VIDAS). Minor macro movement must occur to allow a few extra wires to get in between a pair of macros so that a wiring overflow can be stopped.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

ASCII Representation of Virtual In-Core Model Partitioned Stack

      Chip integrators produce a initial floor plan from all the
available virtual  In-Core Model (VIM) data in the VLSI Interactive
Design Automation System (VIDAS).  Minor macro movement must occur to
allow a few extra wires to get in between a pair of macros so that a
wiring overflow can be stopped.

      The ASCII global interconnect file (Tech) which contains macro
placement can not be easily modified to provide macro adjustments.
Information about the wire regions between the macros is not easily
discernible.

      Stkblk provides the chip integrator with a stack ordering of
the macro placement in the TECH.  The chip integrator can see the
size of the macros and the wire regions between macros.  These two
pieces of information allow the chip integrator to adjust macros with
confidence that overlaps do not occur.
  Step 1: Stkblk reads the VIM which includes the TECH and all
physical
design rules (PHYSICALs) that are called by the TECH.  Portion of a
TECH is shown below:
                USAGE   MACRO   X       Y       MIRROR  ROTATE
                -----   -----   -       -       ------  ------
        PLACE   CC07.R  WBGJ08  3299    6551    N       0
        PLACE   CC06.R  WBGJ08  3299    6528    N       0
        PLACE   CC05.R  WBGJ08  3299    6499    N       0
  Step 2: Stkblk produces the file shown below.  STKBLK is the macro
size in GRIDs.  STKWIRE is the wire regions between the macros in
GRIDs.
          GRID    XLL     YLL     USAGE   MIRROR  ROTATE  KEYWORDS
          ----    ---     ---     -----   ------  ------  --------
  STKBLK  22      3299    6551    CC07.R  N       0
SPINE_OFFSET=0
  STKWIRE 1       3299    6550
  STKBLK  22      3299    6528    CC06.R  N   ...