Browse Prior Art Database

Bus Request Update Mechanism to Improve Processor Performance

IP.com Disclosure Number: IPCOM000116175D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 113K

Publishing Venue

IBM

Related People

Bridges, T: AUTHOR [+3]

Abstract

Disclosed is a mechanism which minimizes unnecessary utilization of a microprocessor's external bus caused by speculative instruction fetches.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Bus Request Update Mechanism to Improve Processor Performance

      Disclosed is a mechanism which minimizes unnecessary
utilization of a microprocessor's external bus caused by speculative
instruction fetches.

      This invention assumes that there exists in the microprocessor
separate functional units which arbitrate for the external
microprocessor bus.  One of these units is an instruction cache unit
which receives requests for instructions from the instruction fetch
unit of the processor.

      Speculative fetches are caused by microprocessor pre-fetch
logic utilizing flow prediction algorithms which predict the flow
that a computer program will take.  These predictions are not always
correct.  The predictions are typically resolved within several
instructions of where they are issued in the instruction stream.
When the actual resolution of the program flow is different than the
predicted flow, then the speculative fetch is not needed and may use
some of the external bus bandwidth unnecessarily.  It is therefore
desirable to minimize the effect of speculative fetches and their
utilization of memory bandwidth.

      There is no issue of performance degradation if speculatively
fetched instructions are already present in a microprocessor's
instruction cache, since the fetching of an instruction from the
cache does not consume any external bus cycles.  However, when
speculative fetching causes an unnecessary external bus access it
reduces the availability of the bus for other system data transfers.
Examples of these data transfers include loads and stores between
memory and the microprocessor's data cache unit, and data transfers
between Direct Memory Access (DMA) devices and system memory on the
external bus.

      The solution to this problem is to allow requests made by the
Instruction Cache Unit (ICU) to the Bus Interface Unit (BIU) to be
removed before the BIU has accepted the request and initiated
external bus activity.  (The BIU will not accept a request from the
ICU if it is already busy handling a bus request from another unit of
the microprocessor, such as the data cache unit or DMA unit).  It is
within this "window of opportunity" that the ICU can remove the
request to the BIU, thereby eliminating what could have been an
unnecessary external bus access.

      Without the control logic associated with this invention, if
the ICU was to issue a request to the BIU,  the ICU would be "locked"
into a state which could only be exited through the acceptance of the
request by the BIU,  and subsequent completion of the bus transfer,
even if the instruction being requested by the ICU was no longer
required by the fetch u...