Browse Prior Art Database

Place Decoupling Capacitances in a Floor Plan

IP.com Disclosure Number: IPCOM000116178D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Fentanes, J: AUTHOR [+4]

Abstract

High chip speeds require more decoupling capacitors than in previous designs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 93% of the total text.

Place Decoupling Capacitances in a Floor Plan

      High chip speeds require more decoupling capacitors than in
previous designs.

      In previous processor designs, decoupling capacitors could be
added manually because the number required was not large.  The new
high decoupling capacitance requirements force unused area on the
chip to be used for decoupling capacitors.  The high volume of
capacitor
placement could be very time consuming for the chip integrator.

      The disclosed process uses a new tool and a critical
enhancement to cplace, the placement tool of the VLSI Interactive
Design Automation System (VLSI) Virtual In-core Model (VIM) database
to place decoupling capacitance quickly and easily in unused space.
  Step 1: Genblk is a new tool that reads the VIM and converts the
chip
active area into blockage.
  Step 2: The circuit row file defines the circuit rows that the
decoupling capacitance will be placed in.  The circuit rows run the
height of the chip and the width of the decoupling capacitor.  The
circuit rows are repeated until the width of the chip is met.
  Step 3: Cplace reads in the circuit row file and the output of
genblk
to place each capacitor into unused space of the chip.  If the
capacitance requirements are high enough, all the unused area could
be devoted to decoupling capacitors.

      The chip integrator is spared from manually placing each
individual capacitor in a graphical editor.  The tedious work can be
replace...