Browse Prior Art Database

Burst Read Off Chip Driver

IP.com Disclosure Number: IPCOM000116183D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Hosokawa, K: AUTHOR

Abstract

Disclosed is a circuit for synchronous DRAM off chip driver which avoids cross over current during data out transition to achieve high speed burst read operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Burst Read Off Chip Driver

      Disclosed is a circuit for synchronous DRAM off chip driver
which avoids cross over current during data out transition to achieve
high speed burst read operation.

      The Figure shows a circuit schematic.  The circuit adds feed
back function to conventional off chip driver.  In a burst read
operation, a DATAIN becomes low and the delayed signal high appears
on NET1 and NET2, and they turn off TP0 and TP1.  At the same time,
NET5 feedbacks low signal to NOR0, and NET3 and NET4 go high to turn
on TN0 and TN1.  In the case the DATAIN becomes high, the delayed
signal appears on NET3 and NET2, and they turn off TN0 and TN1.  NET6
feedbacks high signal to NAND0, and NET1 and NET2 go high to turn on
TP0 and TP1.  Therefore, a crossover current does not appear between
TP0 TP1 and TN0 TN1 transistors.

      This off chip driver is applicable when the driver is required
fast access burst read operation.