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System Clock Corrections for Interrupt-Driven System

IP.com Disclosure Number: IPCOM000116188D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Chen, C: AUTHOR [+3]

Abstract

When the value of system time is maintained jointly by a hardware timer and a microcode interrupt service routine, severe time integrity errors can occur. Assume that system time is maintained as values in two words called "seconds" and "60nanoseconds". The hardware timer is configured to generate a high priority processor interrupt when the input count of 60 nanosecond clock signals reaches a value equal to one second. The timer then automatically resets and begins counting again. Microcode is interrupted and the interrupt service routine increments the value of the "seconds" word by one. The latency associated with this interrupt service routine creates a time integrity exposure to all asynchronous reads of these two system time words.

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System Clock Corrections for Interrupt-Driven System

      When the value of system time is maintained jointly by a
hardware timer and a microcode interrupt service routine, severe time
integrity errors can occur.  Assume that system time is maintained as
values in two words called "seconds" and "60nanoseconds".  The
hardware timer is configured to generate a high priority processor
interrupt when the input count of 60 nanosecond clock signals reaches
a value equal to one second.  The timer then automatically resets and
begins counting again.   Microcode is interrupted and the interrupt
service routine increments the value of the "seconds" word by one.
The latency associated with this interrupt service routine creates a
time integrity exposure to all asynchronous reads of these two system
time words.  Read operations that occur immediately after the
hardware timer has been restarted and before the timer interrupt has
been processed give results that are off by one second.  This
exposure exists because the "60nanoseconds" and "seconds" values are
not updated and captured atomically.

      Since the latency associated with interrupt servicing in this
joint hardware and microcode implementation is unavoidable, a
mechanism to detect the condition was devised.  To prevent the
exposure, the maximum interrupt servicing latency must be known.
Using a timer, ideally the same timer if possible, a flag is set at a
time that is guaranteed to occur after the maximum int...