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Computer Memory Testing using a Specialized Checkerboard Test

IP.com Disclosure Number: IPCOM000116194D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Sarkany, EF: AUTHOR

Abstract

Disclosed is a specialized checkerboard test designed to check for DC write-through disturbs and for data retention failures in computer memory chips. It uses a special three dimensional model of the memory to detect faults not detected by the common two dimensional model tests. The signal timings to the memory chip are set up to stress the chip beyond its worst-case limits.

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Computer Memory Testing using a Specialized Checkerboard Test

      Disclosed is a specialized checkerboard test designed to check
for DC write-through disturbs and for data retention failures in
computer memory chips.  It uses a special three dimensional model of
the memory to detect faults not detected by the common two
dimensional model tests.  The signal timings to the memory chip are
set up to stress the chip beyond its worst-case limits.

      This test utilizes a checkerboard data pattern, which requires
knowledge about the internal cell structure of a memory chip.  In
this case, the physical organization of the 1Kx9 memory was 128x8x9,
i.e., the nine data bits were assigned to sections of 128 words by
eight columns.  This physical cell structure resulted in rather
complex test sequences, as described below, in order to create true
checkerboard patterns.

      To achieve the correct pattern, one can think of the memory as
a three-dimensional array, made up of eight planes which contain 128
nine-bit data words.  When writing a data word to the array, one of
the eight planes is chosen, one of the 128 entries is addressed, and
the nine bits of data are loaded.  Physically, however, the cells are
arranged as slices perpendicular to the eight planes and along a
single data bit.  Hence, bit 0 of the data word at address 0 of the
first plane is physically adjacent to bit 0 of the data word at
address 0 of the second plane, and so forth.  Therefore, to...