Browse Prior Art Database

Instruction Sequence Control for a Super Scalar Processor

IP.com Disclosure Number: IPCOM000116200D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 112K

Publishing Venue

IBM

Related People

Imming, KC: AUTHOR [+2]

Abstract

A method for keeping track of the program order of Reduced Instruction Set Computer/cycles (RISC) instructions in a superscalar processor is disclosed. This solution provides a simple program order "time stamp" that is easy to implement and prove correct.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Instruction Sequence Control for a Super Scalar Processor

      A method for keeping track of the program order of Reduced
Instruction Set Computer/cycles (RISC) instructions in a superscalar
processor is disclosed.  This solution provides a simple program
order "time stamp" that is easy to implement and prove correct.

      In a processor implementation where different processing units
share some common resources, a common control unit must regulate the
flow of instructions through the various pipeline stages.  This
control unit needs to know the status of all instruction in all of
the pipeline stages so it can allocate resources in correct program
order.  This invention provides information to the control unit as to
the relative program order of any two stages of the pipelines.

      A functional unit named IStat (Instruction Status) tracks the
correct program order of every instruction in all of the pipelines.
This unit receives the following signals from each pipeline as
inputs.
  Iack        Instruction dispatch acknowledge.  An instruction was
               dispatched to the first stage of the pipe.
  Offset(0:1) If more that one instruction is dispatched during a
               cycle, the offset indicates the program order of that
               instruction relative to the others dispatched that
same
               cycle.
  Stage1V     Stage 1 valid, The first stage of the pipe holds a
valid
               instruction.
  Stage2V     Stage 2 valid, The second stage of the pipe holds a
valid
               instruction.
  Stg1to2     Instruction has advanced from pipe stage 1 to pipe
               stage 2.

      The ISTAT unit assigns each stage of the pipe a six-bit
relative program counter (RPC) value based on these signals.  To do
this, a 4-bit counter is created that is incremented by one every
cycle that one or more instructions is dispatched.  The ISTAT unit
copies this four-bit counter to the high-order four bits of the RPC
value when an instruction enters that stage of the pipeline.  The
last two bits are assigned an offset value that represents its
relative position among all instructions dispatched that cycle.  This
results in all instructions in the pipeline having a unique RPC
value.  Instructions with a greater value follow instructions with
lesser values in the instruction stream.

      For example, in the following code sequence:
       00000  ld    R1,0(R2)  dispatched cycle 00
       00004  add   R4,R4,R6  dispatched cycle 00
       00008  fpadd F1,F2,F3  dispatched cycle 01
       0000C ...