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Browse Prior Art Database

Very Large Scale Integration Chip Initialization Function

IP.com Disclosure Number: IPCOM000116202D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 134K

Publishing Venue

IBM

Related People

Branstad, MW: AUTHOR [+2]

Abstract

Very Large Scale Integration (VLSI) chip initialization is done with this simple, inexpensive processor that can set chip internal registers, Random Access Memory (RAM), and chip-controlled external Dynamic Random Access Memory (DRAM). Many times, information about the card (amount of memory, what type/level it is) must be relayed to the chip so the system can sense it via its system bus interface. Complex VLSI chip designs are sometimes difficult to set up. This initialization processor can be customized to simplify the task for a given user. As programmable options and function increase, chip registers and memory become more difficult to set up correctly for the user who wants a quickly configured solution. This invention is structured so that all registers and memory are accessible and can be set to any desired value.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 34% of the total text.

Very Large Scale Integration Chip Initialization Function

      Very Large Scale Integration (VLSI) chip initialization is done
with this simple, inexpensive processor that can set chip internal
registers, Random Access Memory (RAM), and chip-controlled external
Dynamic Random Access Memory (DRAM).  Many times, information about
the card (amount of memory, what type/level it is) must be relayed to
the chip so the system can sense it via its system bus interface.
Complex VLSI chip designs are sometimes difficult to set up.  This
initialization processor can be customized to simplify the task for a
given user.  As programmable options and function increase, chip
registers and memory become more difficult to set up correctly for
the user who wants a quickly configured solution.  This invention is
structured so that all registers and memory are accessible and can be
set to any desired value.  This is particularly useful for things
that are set up once, such as memory management structures, interrupt
levels, memory controller configuration, chip interface control, etc.

      The initialization processor (IP) begins execution just after
the VLSI has completed its flush sequence.  It will execute inline
instructions that only do data writes to memory elements (chip
registers, controller DRAM).  If no erasable programmable read-only
memory (EPROM) is present (as it is optional), a stop instruction
will be executed if ones appear in the top two bits of the 8 bit
flash data bus.  This can be done with pullups.  If an EPROM is
present, it will first fetch the opcode, then the address, then as
much data as is needed.  Even though flash is fairly slow access
times, some performance items have been added that are inexpensive to
implement, such as accesses cycles that only toggle the address for
more data, and overlapping of instruction execution with the next
data fetch from the EPROM.  More complex instructions are supported
that loop on an indexed address, data, or both.  The need for this
function, for example, is to write a data pattern in a large DRAM
bank.  This can be done with one instruction and is performed at much
faster speed than individual processor accesses.

      Fig. 1 is a block diagram of how the process flow works.
Basically, once the instruction is fetched and decoded, a signal is
sent to the VLSI chip central address decoding logic to execute the
command, also with the address and write data along with it.  The
cycle runs until an acknowledgment comes back from the decoding logic
that indicates that the transfer has completed.  The processing unit
then decides if another instruction is to be executed or stop
execution.  A status bit is set when the processor is done.  Since
this function has access to chip registers, it could program an
interrupt to the system bus when processing is done.

      Fig. 2 is the list of supported initialization instructions
that will be fetched from the external EPROM...