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Placement Optimization using a Graphical Placement Tool in the VLSI Interactive Design Automation System Database

IP.com Disclosure Number: IPCOM000116212D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Demaris, D: AUTHOR [+3]

Abstract

The graphical placement tool (VIGR) in the VLSI Interactive Design Automation System (VIDAS) toolset is coupled with the VIDAS placement tool (CPLACE) to optimize an area in the floor plan.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 89% of the total text.

Placement Optimization using a Graphical Placement Tool in the VLSI
Interactive Design Automation System Database

      The graphical placement tool (VIGR) in the VLSI Interactive
Design Automation System (VIDAS) toolset is coupled with the VIDAS
placement tool (CPLACE) to optimize an area in the floor plan.

      CPLACE could not guarantee that a macro assigned to a
designated area would be placed in that area, therefore a macro group
file is created allowing the group to be placed in a certain area.
Once CPLACE has partitioned the rest of the chip, use VIGR to
optimize the grouped macros within the group area relative to the
remaining macros in the floor plan.

      Step 1: Decide with macros need to be grouped for a designated
area.  Creation of the group file allows all the macros to be placed
in the designated area as an entity.

      Step 2: CPLACE will partition all macros not included in the
group and leave the group ordering alone.

      Step 3: Create an area in VIGR that encompasses the group
created in Step 1.  Run the optimize program in VIGR.  VIGR will fix
all macros outside the group area and then invoke CPLACE to partition
and optimize the macros in the group area relative to the fixed
macros.  Upon completion of CPLACE, the option of saving the results
can be accomplished within VIGR.

      Chip integrators can now follow logic designers instructions by
placing macros in a predefined area because of RC timing delay.  VIGR
...