Mechanism for Aliasing and Snoop Invalidates in Semi-Associative Caches
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Barrera, DD: AUTHOR [+3]
A method for eliminating the second cycle access in a semi-associative instruction cache is disclosed. This reduces cache control and core complexity.
Mechanism for Aliasing and Snoop Invalidates in
A method for
eliminating the second cycle access in a
semi-associative instruction cache is disclosed. This reduces cache
control and core complexity.
invention capitalizes on the non-coherence and non-store
nature of an instruction cache to produce a less complex and faster
Semi-associative cache implementation. In this invention, the second
cycle access is eliminated. An aliased entry is written into a line
in the CAMlet, even though that data (with the same real tag) may
reside in the CAMlet with a different Effective address CAM (ECAM)
address tag. Thus, two entries can exist in the cache with the same
Real Address (RA) if they where accessed using different effective
addresses (EAs). Since multiple entries for a given RA are allowed,
there must be a method for invalidating all of these entries when
this RA is invalidated by cache invalidate instructions which must be
based on real addresses. This invention provides a a method for
doing this in parallel with normal cache read and write operations.
performing the second cycle access after a first cycle miss
when the real cache line may exist in another line of the CAMlet may
seem to be a performance penalty. It actually is not if cache hit
ratios are high to L1 and/or L2 cache since doing a second cycle
accesses increases the latency to retrieve aliased entries in the
cache. In this invention,...