Browse Prior Art Database

Dual Self-Reset Differential Driver

IP.com Disclosure Number: IPCOM000116223D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 87K

Publishing Venue

IBM

Related People

Cao, T: AUTHOR [+5]

Abstract

A program is disclosed which addresses the problems of self-resetting dynamic logic signals which are not suitable for transmission between communicating chips and a low-voltage differential waveform which is desired for communications between chips in special performance sensitive applications.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Dual Self-Reset Differential Driver

      A program is disclosed which addresses the problems of
self-resetting dynamic logic signals which are not suitable for
transmission between communicating chips and a low-voltage
differential waveform which is desired for communications between
chips in special performance sensitive applications.

      Fig. 1 shows the overall schematic consisting of a data in to
data out section where the data in pulses are labeled as: T , C, T_ ,
C_  which represent the self resetting dynamic logic input signals.
These signals are converted to the low voltage differential output
signals labeled: OUT & OUT_.

      The schematic is believed to be novel because self resetting
dynamic logic is not commonly known or used in the industry.

      Fig. 2 shows a blowup section from Fig. 1 focusing on the data
in to data out path for the left side of the Fig. 1 schematic.  The
left and right sides are mirror images of one another differing only
in the input and output signals.

      Fig. 3 shows the select circuitry and reference voltage
generation circuitry used to provide the reference voltage to the
gate of N-type transistor Q72.  Input signals E0 & E2 are decoded
such that the OUT & OUT_ signals are in a high impedance state in all
cases except the case: E0=1 & E2=1.  When E0=1 & E2=1 this circuitry
enables the output driver by establishing a critical reference
voltage at the gate of Q72 thru pass devices Q15 & Q18.  Device Q...