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Browse Prior Art Database

Etch Process for Shallow Isolation Trench

IP.com Disclosure Number: IPCOM000116237D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Coronel, P: AUTHOR [+2]

Abstract

Disclosed is a two-step dry-etch process designed to improve the quality of the shallow trenches that are used to isolate the FET devices in 16-Mbit DRAM chips. Isolation Trenches (IT) are formed at the IT mask level.

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Etch Process for Shallow Isolation Trench

      Disclosed is a two-step dry-etch process designed to improve
the quality of the shallow trenches that are used to isolate the FET
devices in 16-Mbit DRAM chips.  Isolation Trenches (IT) are formed at
the IT mask level.

The state of the art NF3/N2 chemistry has revealed a number of
defects such as:
  1.  silicon and nitride remainings which create surrounding
disturbed
       fails;
  2.  possible negative profiles;
  3.  mask deformation at wafer edge along with degradation of the
TEOS
       collar remaining; and,
  4.  topography (collar) discontinuities during the etch who creates
       seams during the TEOS fill step.

      Basically, the disclosed two-step process comprises a first
step which uses a low-pressure NF3/N2/CHF3 chemistry, followed by a
very selective second step which is based on CHF3/Ar/CF4 chemistry.
Fig. 1 illustrates the trench profile after the first etch step has
been performed.

      Because the oxide/nitride selectivity is different to 1, this
first step leaves a discontinuity in the shape (at the bottom) due to
the collar.  To ensure TEOS fill without any seam or stress, the
second step is performed by using a CHF3/Ar/CF4 chemistry at
low-pressure.  As a result, a very selective behavior is created
which eliminates the topography concerns.  In particular, in the
second step, CHF3 increases nitride etch rate, so that nitride nodes
are etched faster than sil...