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Hysteresis CMOS Differential Circuit

IP.com Disclosure Number: IPCOM000116240D
Original Publication Date: 1995-Aug-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Cao, T: AUTHOR [+4]

Abstract

High performance CMOS microprocessor systems technologies have evolved to lower power supply voltage operation and increased chip circuit densities so as to create an increased noise environment while attempting to communicate with lower voltage signals thus posing a difficult design challenge. Figure 1. A CMOS differential circuit with hysteresis

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Hysteresis CMOS Differential Circuit

      High performance CMOS microprocessor systems technologies have
evolved to lower power supply voltage operation and increased chip
circuit densities so as to create an increased noise environment
while attempting to communicate with lower voltage signals thus
posing a difficult design challenge.  Figure 1.  A CMOS differential
circuit with hysteresis

      This disclosure provides a novel receiver circuit that has
hysteresis properties for receiving single-ended signals onto a CMOS
chip such that noise immunity and functional reliability is improved.

      Some prior art techniques are shown in the schematic in Fig. 1.
The same technique addresses the same problem as this disclosure and
also uses a differential circuit as part of the schematic to process
the signal from a single-ended source.  The differential circuit in
Fig. 1 consists of transistors T1, T2, T3, T4, and T5.  A non
inverting buffer consisting of T8 and T9 takes the input signal and
feeds it to the reference side of the differential circuit.  The
signal at the "REF" node, however, is reduced in amplitutde as
follows:
  A up level or logical "1" voltage is VIN-VTn= 2.2-0.8=1.4 volts.
  A down level or logical "0" is VIN-VTp=0.2-(-0.8)=1.0 volts.

      It is this change of reference voltage that produces a
hysteresis effect or band on the switching point of the circuit so as
to make the circuit require more signal voltage at the gate of the
input transistor T4 to...